To provide a semiconductor integrated circuit and layout design method thereof for relaxing wiring congestion by effectively utilizing interconnection resources around a hard macro while using slant interconnections in a layout design step in particular regarding the layout design method of the semiconductor integrated circuit.

The semiconductor integrated circuit of the present invention comprises a hard macro 10 including a plurality of pins P of minimum line width (c) disposed to be positioned while being obliquely deviated from each other at minimum intervals (a) on one side of the hard macro, and slant interconnections N connected to the pins in the hard macro. The pins are obliquely disposed inside the hard macro. Access can be performed directly from longitudinal and lateral interconnections arranged side by side at minimum intervals, and access can also be performed directly from slant interconnections arranged side by side at minimum intervals.