SEMICONDUCTOR MEMORY DEVICE AND SYNCHRONISM TYPE SEMICONDUCTOR MEMORY DEVICE

Japanese Patent JP2938706

B2

PURPOSE: To provide a multifunctional synchronism type semiconductor memory device which is small in a chip area, fast, and low in power consumption.
CONSTITUTION: Memory arrays 6a and 6b are divided into banks which can independently operate and the respective banks #1 and #2 are provided with registers 10a and 10b for read data storage and registers 16a and 16b for write data storage which independently operate. The memory arrays are divided into small array blocks, and local IO lines are arranged corresponding to the respective array blocks and connected to a global IO line, which is connected to a preamplifier groups 8a and 8b and write buffer groups 14a and 14b. Control signal generating circuits 20 and 22 and a register control circuit 28 delay the timing of the writing inhibition of only a desired bit at the time of continuous writing operation, batch writing to a selected memory cell at the point of time of final data input when data writing is interrupted with less than lap length in the successive writing, and the activation of the memory array when a write cycle is repeatedly executed.

KONISHI YASUHIRO
MYAMOTO TAKAYUKI
KAJIMOTO TAKESHI
IWAMOTO HISASHI

JP8459193A

August 25, 1999

April 12, 1993

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MITSUBISHI DENKI KK

G06F12/06; G06F12/00; G11C7/00; G11C11/401; G11C11/407; G11C11/408; G11C11/409; G11C11/41; G11C11/413; H01L21/8242; H01L27/108; (IPC1-7): G11C11/407; G11C7/00; G11C11/401; G11C11/408; G11C11/409; G11C11/41; G11C11/413; H01L21/8242; H01L27/108

JP684351A
JP5334867A
JP6318391A

Fukami Hisaro (3 outside)

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