SEMICONDUCTOR MEMORY AND ITS MANUFACTURING METHOD

Title:

SEMICONDUCTOR MEMORY AND ITS MANUFACTURING METHOD

Document Type and Number:

Japanese Patent JP2002230991

Kind Code:

A

Abstract:

To reduce a leak electric power at the time of standby and to improve the yield in manufacturing.

This memory is provided with a plurality of memory cells 1211-12mn, arranged in a matrix state consisting of rows and columns, cell power source supply lines 131-13m, 141-14n connected so that a drive current is supplied commonly to memory cells belonging to the rows or the columns, a plurality of pieces of current detecting means 161-16m, 231-23m for detecting a current flowing in these cell power source supply lines, detected result read-out means 17, 24 reading out a current detected result detected by these current detecting means, means 151-15m, 221-22n cutting off a drive current flowing in the cell power source supply line based on the output of this means 17 or 24.

Inventors:

SAKURAI TAKAYASU
KAWAGUCHI HIROSHI
KANDA KOICHI

Application Number:

JP2001028631A

Publication Date:

August 16, 2002

Filing Date:

February 05, 2001

Export Citation:

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Assignee:

FOUND PROMOTION IND SCIENCE

International Classes:

G11C11/413; G11C29/00; G11C29/04; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; G11C11/413

Attorney, Agent or Firm:

Norio Ogo (2 outside)

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