To provide a redundant decoder circuit and a semiconductor memory provided with the circuit.

The redundant decoder circuit includes the array of a plurality of electrically erasable and programmable memory cells which store a pair of complementary address data corresponding to a cell having defect of a main memory cell array, which is connected respectively to corresponding bit lines out of one word line and a plurality of bit lines, a word line driver outputting voltage corresponding to read-out, erasure, and program modes and driving a word line, a pre-charge circuit pre-charging a first node, an output circuit latching a voltage level of the first node and outputting it to an information signal, and a comparing unit corresponding respectively to a pair of complementary data bits out of a pair of complementary address data.