PURPOSE: To incorporate memory cells into the same chip and to make an internal data transfer possible by connecting the bit line connected to a nonvolatile memory cell and the bit line connected to a volatile memory cell via a transfer gate.

CONSTITUTION: The bit lines 2 and 3 of volatile memory cells 4 and 5 and the bit lines 9 and 10 of nonvolatile memory cells 11 and 12 are connected mutually by transfer gates 7 and 8. Then, the opening and closing of the transfer gates 7 and 8 are controlled by signals 1 and 2 and accesses to the memory cells 4, 5, 11 and 12 are individually and optionally made. Thus, the memory cells 4, 5, 11 and 12 are incorporated into the same chip and data transfers between the memory cells 4 and 5 and the memory cells 11 and 12 are performed on the bit line in the chip. Further, as for the nonvolatile memory cell and the volatile memory cell the memory cell of a flash EEPROM and the memory cell of a DRAM are respectively preferable.