Title:
FAST PROGRAM, AND FAST SWITCHING METHOD TO VERIFYING PROGRAM
Document Type and Number:
Japanese Patent JP2002230988
Kind Code:
A
Abstract:
To provide a program and a new method for verifying a program.
The threshold voltage of a memory cell is increased by the minimum charge and discharge of bit lines and control gate lines, and successively, the voltage is measured. Also, the capacity between the bit lines and the control gate lines is used to reduce the number of required voltage references. A program current is reduced by using a load device connected to a source diffusion region. Consequently, the band width of a program is increased by a low current consumption of a high voltage charge pump.
Inventors:
OGURA SEIKI
OGURA TOMOKO
OGURA NORI
OGURA TOMOKO
OGURA NORI
Application Number:
JP2001381765A
Publication Date:
August 16, 2002
Filing Date:
December 14, 2001
Export Citation:
Assignee:
HALO LSI DESIGN & DEVICE TECH
International Classes:
G11C16/02; G11C16/04; G11C16/06; G11C16/12; G11C16/34; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/04; G11C16/02; G11C16/06; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Kazuki Tanaka (2 outside)