SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF

Title:

SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF

Document Type and Number:

Japanese Patent JPH04262573

Kind Code:

A

Abstract:

PURPOSE: To obtain a transistor having an LDD structure optimally adapted for both a memory cell array and a peripheral circuit in a semiconductor memory using the transistor having the LDD structure.

CONSTITUTION: When a transistor having an LDD structure is formed, sidewall protective film 7 common for a memory cell array forming region 12 and a peripheral circuit forming region 11 is formed, and only the film 7 of the region 11 is anisotropically etched thereby to form a side protective film 20 having a narrower forming width than the film 7, and LDD regions 50A (60A) and 50B having different forming widths are respectively obtained on the regions 12 and 11. Since the forming widths of the optimum LDD regions can be respectively set in the regions 12 and 11, the transistors having the optimum LDD structures can be obtained for both the array and the peripheral circuit.

Inventors:

ONODA HIROSHI

Application Number:

JP2307591A

Publication Date:

September 17, 1992

Filing Date:

February 18, 1991

Export Citation:

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Assignee:

MITSUBISHI ELECTRIC CORP

International Classes:

H01L27/10; H01L21/336; H01L27/108; H01L29/78; (IPC1-7): H01L21/336; H01L27/108; H01L29/784

Attorney, Agent or Firm:

Takeo Takeo (1 person outside)

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