Title:
SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2008078404
Kind Code:
A
Abstract:
To provide a semiconductor memory having a structure capable of laminating a memory layer without a significant increase of process.
The semiconductor memory has active areas (AA) of the shape of stripes laminated in parallel to a substrate; each of these areas AA laminated perpendicularly to the substrate is processed self-alignedly; each AA uses one side or both of the sides perpendicular to the substrate as a channel region and each AA crosses at right angle with a plurality of gate electrode (GC) in the longitudinal direction; a portion crossing at right angle of AA and GC forms a memory cell, and a plurality of cells in the plane crossing at right angle shares the gate electrode.
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Inventors:
KIYOTOSHI MASAHIRO
OZAWA YOSHIO
YAMAMOTO AKITO
ARAI FUMITAKA
SHIRATA RIICHIRO
OZAWA YOSHIO
YAMAMOTO AKITO
ARAI FUMITAKA
SHIRATA RIICHIRO
Application Number:
JP2006256194A
Publication Date:
April 03, 2008
Filing Date:
September 21, 2006
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/8247; H01L27/10; H01L27/105; H01L27/115; H01L29/788; H01L29/792; H01L45/00; H01L49/00
Domestic Patent References:
| JP2008042206A | 2008-02-21 | |||
| JP2006155750A | 2006-06-15 | |||
| JP2004152893A | 2004-05-27 |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto