PURPOSE: To obtain a semiconductor memory which can output read-out data from a memory cell to a pre-sense amplifier at high speed.
CONSTITUTION: Pre-sense amplifiers 24 are provided for each plural pairs of bit line BL, the inverse of BL of a cell array 23. The amplifier 24 detects a state of pairs of bit lines by converting a potential difference between the bit line BL and the inverse of BL to a current ratio based on an address variation detecting signal ATD. Emitters of transistors Q1a, Q2a of a global sense amplifier 25 are connected to resistors R1, R2 respectively, collectors are connected to ground GND through constant current sources 11, 12, while connected to plural amplifiers 24 through a bus line GB, the inverse of GB. The global sense amplifier 25 converts a current flowing in the transistors Q1a, Q2a to voltage, and outputs output signals VOUT, the inverse of VOUT from sources of transistors TN11, TN 12.
FURUKAWA CHIAKI
YAMAGUCHI SHUHEI
UKAI HIROAKI
FUJITSU VLSI LTD