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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS62299000
Kind Code:
A
Abstract:

PURPOSE: To read and write the data from an external part to a memory cell in a conductor redundant bit array by disabling an error detecting signal by a control signal from an external part and selecting simultaneously the bit line connected to the memory cell in a redundant bit array with a selector circuit.

CONSTITUTION: When the control signal ECCSTP of an ECC function stoppage is enabled, a coding circuit 4 and an error detecting circuit 5 are not usually operated, the output B of the coding circuit 4 comes to be a high impedance condition and inspection information is not inputted to a redundant bit array. An error detecting signal ED, which is the output of the error detecting circuit 5 comes to be a disabling condition and the information in a memory cell is sent through an input/output circuit 7 to the external part as it is. On the other hand, a selector circuit 3 not only can select a bit line connected to the memory cell in the information bit array, but also can select bit lines A and A' connected to the inside of the redundant bit array. Consequently, optional data can be written and read.


Inventors:
KOTANI HISAKAZU
Application Number:
JP14191586A
Publication Date:
December 26, 1987
Filing Date:
June 18, 1986
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L27/10; G11C11/34; G11C11/413; G11C29/00; G11C29/42; (IPC1-7): G11C11/34; G11C29/00; H01L27/10
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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