Title:
SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC EQUIPMENT AND SEMICONDUCTOR MODULE
Document Type and Number:
Japanese Patent JP2008135763
Kind Code:
A
Abstract:
To improve reliability in interlayer connection while suppressing the enlargement of the chip size.
Trenches 4a-4c are provided at the position of a scribe line SL of semiconductor substrates 1a to 1c, and after the substrates 1a to 1c are laminated, a conductive material 11 is filled inside the trenches 4a to 4c provided at cut-sections of the substrates 1a to 1c.
Inventors:
YAMAGUCHI KOJI
Application Number:
JP2007329011A
Publication Date:
June 12, 2008
Filing Date:
December 20, 2007
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H01L23/12; H01L21/3205; H01L23/52; H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Yasuhiro Bono
Yoshiaki Naito
Yasuhiro Bono