Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3204200
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve access speed of the memory as a whole by speeding up the access of a redundancy cell array.
SOLUTION: In a semiconductor memory device having a normal cell array and a redundancy cell array, if the normal cell array which is the object of substitution to the redundancy cell array, is selected the first circuit 8 outputs a one shot signal PBLST to a block hunting circuit 7, which activates a precharge stop signal without waiting for the decision result whether the redundancy cell array outputted from a decoder 4 is in a selective state, making the reducnancy cell array a selective state once.
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Inventors:
Naohiko Sugibayashi
Application Number:
JP4327798A
Publication Date:
September 04, 2001
Filing Date:
February 25, 1998
Export Citation:
Assignee:
NEC
International Classes:
G11C29/04; G11C29/00; (IPC1-7): G11C29/00
Domestic Patent References:
| JP628888A | ||||
| JP6139797A | ||||
| JP6376197A |
Attorney, Agent or Firm:
Masaki Yamakawa
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