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Patent Searching and Data


Title:
SEMICONDUCTOR TEST APPARATUS AND SEMICONDUCTOR TEST METHOD
Document Type and Number:
Japanese Patent JP2005166942
Kind Code:
A
Abstract:

To provide a semiconductor test apparatus at a low cost capable of properly evaluating a semiconductor at a temperature of about 400 °C such as an EM evaluation.

Through-holes for exposing pads of each of dies of a semiconductor wafer 5 in a state that the semiconductor wafer 5 is mounted on a measurement substrate 1 are formed to the measurement substrate 1, the semiconductor wafer 5 is supported on one side of the substrate 1 by a wafer holder 12, a wire pattern used for transmitting evaluation test signals to the supported semiconductor wafer 5 is formed to the other side of the board, in a state that the pads of each die and pads of the wire pattern are wire-bonded through the through-holes, the measurement substrate 1 is set at the evaluation test so that the semiconductor wafer mount part of the substrate 1 is placed inside a high temperature oven 101 and terminal parts to which the evaluation test signals are applied are located outside the temperature oven 101.


Inventors:
OI KENICHI
CHITEN HIRONORI
Application Number:
JP2003403544A
Publication Date:
June 23, 2005
Filing Date:
December 02, 2003
Export Citation:
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Assignee:
ESPEC CORP
International Classes:
H01L21/66; G01R31/26; G01R31/28; H01L23/58; H01L29/10; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Kenzo Hara