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Title:
SHARED MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH0594379
Kind Code:
A
Abstract:

PURPOSE: To improve the usefulness of a system when a fault is generated at a shared memory between processors.

CONSTITUTION: In the case of setting an FFA (operation continuation mode flip-flop) 120, in write access, only when the fault is generated at both memory access, the fault is informed of a memory access control means 105, and the access is abnormally finished. Concerning read access, when the fault is detected at one memory access, access destination switching is instructed to the memory access control means 105, and normal memory data are read out. On the other hand, the fault state of the memory is held in FFB (error holding flip-flops) 108 and 109, and the access to the memory temporarily generating the fault is forcedly defined as the fault afterwards.


Inventors:
TAKAHASHI ATSUSHI
Application Number:
JP25329491A
Publication Date:
April 16, 1993
Filing Date:
October 01, 1991
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
G06F12/16; (IPC1-7): G06F12/16
Attorney, Agent or Firm:
Uchihara Shin



 
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