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Title:
SHIELDED PACKAGE FOR SURFACE MOUNTING COMPONENT
Document Type and Number:
Japanese Patent JPS6430297
Kind Code:
A
Abstract:

PURPOSE: To facilitate coexistence of a digital circuit and an analog circuit on a mother board and improve a reliability and universality by a method wherein conductor pattern are provided as the front and rear layers of an outermost layer so as to cover the whole layer surfaces except the parts necessary for terminals, contact through-holes and the like for connection of electronic components and the front and rear conductor layers are used as a component mounting layer and an electric source layer.

CONSTITUTION: A shielded package 100 for surface mount components are composed of a multilayered printed wiring board 1, conductor pins 33, surface mount components 40 and a cap 50 for shielding. On the surface sides of a multilayer interconnection board 1, outer conductor layers 61 and 62, which are the electric source layers of the multilayered printed wiring board 1, are provided. The outer conductor layers 61 and 62 are so formed as to cover the whole layer surfaces except the parts necessary for terminals, contact through-holes and the like for connection of electronic components. With this constitution, conductor patterns for signal transmission are provided between the electric source layers so that a shielding effect can be improved.


Inventors:
TAKAHASHI SHINJI
YASUE TOSHIHIKO
HIRABAYASHI KIMITAKA
Application Number:
JP18705687A
Publication Date:
February 01, 1989
Filing Date:
July 27, 1987
Export Citation:
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Assignee:
IBIDEN CO LTD
International Classes:
H05K9/00; H05K1/00; H05K1/02; (IPC1-7): H05K9/00
Domestic Patent References:
JPS6266652A1987-03-26
Attorney, Agent or Firm:
Hironori Takenori



 
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