Title:
集積回路におけるホットキャリア効果のシミュレーション方法
Document Type and Number:
Japanese Patent JP4066399
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method that simulates a hot carrier effect in an IC at a circuit level. SOLUTION: A hot carrier timing library 106 having the delay data of each cell is generated from IC cell data 102, and timing data 112 after scaled deterioration is generated by using the library 106. Then, a logic simulator 114 and a timing analyzer 116 simulate the operation of an IC by using the data 112. The data 112 is generated on the basis of the cell delay data and the switching frequency of each cell in each time.
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Inventors:
Jin Kun Fan
Hirokazu Yonezawa
Refen Woo
Yoshiyuki Kawakami
Iwanishi Shinbo
Alvin Chen
Norio Koike
Pin chain
Chun Shin Ye
Chi Hong Liu
Hirokazu Yonezawa
Refen Woo
Yoshiyuki Kawakami
Iwanishi Shinbo
Alvin Chen
Norio Koike
Pin chain
Chun Shin Ye
Chi Hong Liu
Application Number:
JP14616599A
Publication Date:
March 26, 2008
Filing Date:
May 26, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; G06F17/00; G06F19/00; H01L21/66; H01L21/82; H01L21/8234; H01L27/088; H01L29/00
Domestic Patent References:
| JP11135388A | ||||
| JP9292436A | ||||
| JP9330344A | ||||
| JP10228497A | ||||
| JP10124565A | ||||
| JP10134096A |
Other References:
Yonezawa, H. et al. ”Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits”, IEDM ’98 Technical Digest., IEEE, 平成10年12月, p.93-96
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Koyama