To provide a software simulator for a processor capable of easily returning to a halfway state of an instruction execution process after the instruction of a program to be debugged is executed.

Each time an instruction is carried out, a software simulator makes the resource values of a register model and a memory model held by a state information file 6. Furthermore, when an instruction for returning to a state for only one instruction is inputted after the instruction is executed, it returns the resource values of the register model and the memory model to the previous state for only one instruction from the current state on the basis of the contents of the file 6.