Title:
STEREOPHONIC AND DUAL VOICE RECOGNITION CIRCUIT
Document Type and Number:
Japanese Patent JP3479334
Kind Code:
B2
Abstract:
PURPOSE: To decrease the number of pins of a chip and to reduce the stray capacity of a signal system by removing a capacitor for signal transmitter interposed between an AM amplifier and an amplifier and using a ground type capacitor.
CONSTITUTION: An FM detector 100 detects an FM wave. A BPF 200 filters the FM-detected signal to detect a specific pilot signal. The AM detector 300 detects an AM wave modulated into the pilot signal. A capacitor 600 reduces a DC component superposed on the detected AM wave in an amplifier 400. The amplifier 400 amplifies the output signal of the AM detector 300 and the AM wave of the detected AC component. Namely, the capacitor 600 is coupled between the common node of a resistance 500 and the amplifier 900, and a ground voltage so as to hold a proper DC level of the amplifier 400 even if the output of the detector 300 varies, and then the output signal of the amplifier 400 and the signal from the common node are used as an input to a phase detector 900, so that the DC component can be removed.
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Inventors:
Equipment Hana
Application
Application
Application Number:
JP221094A
Publication Date:
December 15, 2003
Filing Date:
January 13, 1994
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G10L15/10; H03D1/22; H04B1/16; H04B1/26; H04H40/36; H04S1/00; H04S5/00; H04H1/00; (IPC1-7): H04H5/00; H04B1/16; H04B1/26
Domestic Patent References:
| JP5582572A | ||||
| JP56110387A | ||||
| JP55140374A | ||||
| JP55110481A | ||||
| JP6268617A |
Attorney, Agent or Firm:
Masaki Hattori
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