PURPOSE: To shorten the cycle of storage of required state information without increasing a memory capacity, by dividing memories to long-cycle memories and short-cycle memories to store state information in them.

CONSTITUTION: State information which is changed quickly is connected to a memory 31, and state information which is changed slowly is connected to a memory 32. A clock 74 for storage of the memory 32 is connected to one bit of the memory 31. A control logic 6 generates clocks 71, 72, 74, and 75 periodically, and state information is stored in the memory 31 by the clock 71, and state information is stored in the memory 32 by the clock 74. The storage operation is stopped by stopping clocks 71, 72, 74, and 75. In case of the read of contents of memories, a clock 73 is outputted from the logic 6 to read out contents of memories 31 and 32 to a register 10. Though read-out contents have a time difference because of the difference of storage cycle, they are stored in the memory 31. Thus, the time series is matched by the clock 74 for storage of the memory 32.