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Title:
SUBSEQUENT ROUTE SWITCHING SYSTEM FOR NETWORK SYNCHRONIZING DEVICE
Document Type and Number:
Japanese Patent JPH0230299
Kind Code:
A
Abstract:

PURPOSE: To device the system such that a normal high-order link is to be immediately switched by selecting a clock signal extracted from a low-order link and giving the signal to phase synchronizing oscillator if a relay terminal station accommodating the high-order link causes a fault signal.

CONSTITUTION: High-order group digital links 1a, 1b are converted into primary digital links 5a-5d of low-order at relay terminal stations 2a, 2b and signals 4a, 4b are sent at the fault of the high-order group. Clocks 9a, 9b are extracted from the primary links 5a, 5c at link accommodation device 6a, 6c and inputted to a network synchronizing device 8 together with the fault signals 4a, 4b. The network synchronizing device 8 has gate circuits 10a, 10b, and if a link 1a outputs a fault signal 4a, the gate 10a is reset to energized a monitor circuit 11a and a switching control circuit 12, a changeover circuit 13 selects the gate 10b to give a clock 9b to the phase synchronizing oscillator 14 and to give a clock signal 15 to a time division converter. Thus, the synchronization with high accuracy is always kept.


Inventors:
SHIMAZAKI SHIGEKI
Application Number:
JP17911688A
Publication Date:
January 31, 1990
Filing Date:
July 20, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04M3/22; H04J3/06; H04L7/00; H04Q11/04; (IPC1-7): H04J3/06; H04L7/00; H04M3/22; H04Q11/04
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)



 
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