Title:
SUBTRACTOR CIRCUIT
Document Type and Number:
Japanese Patent JP3260183
Kind Code:
B2
Abstract:
PURPOSE: To attain the subtraction in a small constitution and with high accuracy and at the same time to easily attain various arithmetic forms by connecting plural capacity connections to plural inverters in series and specifying the connection of the input and output terminals.
CONSTITUTION: The voltage V1 and V01 are supplied to a 2-input capacity connection CP1 and then the voltage V2 is supplied to the connection CP1 via a capacitance C2. The connection CP1 connects the capacitances C1 and C01 in parallel to an inverter INV1. The capacitance C2 is connected to the INV1 in parallel to the capacitance C1 and C01. Then the output of the INV1 is fed back by a feedback circuit EC via the capacitance C01. Meanwhile the voltage is supplied to another 2-input capacity connection CP2 through an output terminal of the INV1 and then the voltage V3 is supplied to the capacity connection CP2 via a capacitance C3. The capacity connection CP2 connects the capacitances C02 and C03 in parallel to an inverter INV2 and defines the output voltage of the INV2 as the result of subtraction.
Inventors:
Kotobuki Guoliang
Yang Yasuyasu
Wiwat Wonwalla Wipat
Nao Takatori
Makoto Yamamoto
Yang Yasuyasu
Wiwat Wonwalla Wipat
Nao Takatori
Makoto Yamamoto
Application Number:
JP32740892A
Publication Date:
February 25, 2002
Filing Date:
November 12, 1992
Export Citation:
Assignee:
Takayama Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
G06G7/14; (IPC1-7): G06G7/14
Domestic Patent References:
| JP58127271A | ||||
| JP1258188A | ||||
| JP5988756U |
Other References:
【文献】永田穣「IC演算増幅器とその応用」日刊工業新聞社(S53.1.30)p.11~17
Attorney, Agent or Firm:
Makoto Yamamoto