Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SUPERCONDUCTION DELAY LINE MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6139999
Kind Code:
A
Abstract:

PURPOSE: To make large delay time per unit wiring length at a delay line part and to make small the delay time at wiring of a peripheral circuit part by prescribing film thickness of an earth plate at a superconduction transmission line in accordance with a corresponding area.

CONSTITUTION: A signal line 10, a control line 7, etc., of a peripheral circuit, which are linked through a superconduction transmission line 4, earth plates 2 and 11 of the line 4, the line 4 and a Josephson junction 8, are laminated on a substrate 1 together with insulation layers 3, 5 and 9. Film thickness of an area part 2 in correspondence to the line 4 of the earth plate is thinner compared with an area part 11 in correspondence to a peripheral circuit forming part, and an essential magnetic permeability in proportion to the delay time of the part becomes larger. Consequently, the delay time per unit wiring length at a delay line part becomes larger, the delay time at wiring of a peripheral circuit part becomes smaller, and a repeating frequency of the signal can be enhanced and a superconduction delay line memory device with large memory capacity can be obtained.


Inventors:
NAGAI HAJIME
Application Number:
JP16049884A
Publication Date:
February 26, 1986
Filing Date:
July 31, 1984
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G11C21/00; G11C11/44; H01L39/22; (IPC1-7): G11C11/44; G11C21/00
Attorney, Agent or Firm:
Uchihara Shin