Title:
SYNAPSE ELEMENT
Document Type and Number:
Japanese Patent JP2019161068
Kind Code:
A
Abstract:
To provide a novel three-terminal analog operation element for implementing large-scaled synapse calculation for neuro-morphic learning.SOLUTION: An MOSFET element 10 having a laminated structure of amorphous oxides is an MOS capacitor structure consisting of a metal electrode 18, two kinds of insulation films 15 and 17, an interface dipole modulation mechanism 16, and an interface of the insulation film 15 and a semiconductor 14. In the MOSFET element 10, a dipole is modulated by an electric field applied to the interface dipole modulation mechanism 16, such that a threshold voltage is continuously changed. A pre-neuron spike 19 and a post-neuron spike 20 are inputted to the MOSFET element 10 with a time difference, such that a potential change in the MOS structure corresponding to the time difference occurs, and the change is read out as a change of a channel current. Thus, synapse spike timing-dependent plasticity is realized.SELECTED DRAWING: Figure 1
Inventors:
MIYATA NORIYUKI
Application Number:
JP2018047138A
Publication Date:
September 19, 2019
Filing Date:
March 14, 2018
Export Citation:
Assignee:
AIST
International Classes:
H01L27/10; G06G7/60; G06N3/04; G06N3/063; H01L27/1159