Title:
SYNCHRONISM JUDGMENT CIRCUIT AND TELEVISION RECEIVER
Document Type and Number:
Japanese Patent JP3675050
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To judge that a video signal where a vertical synchronizing signal is easily missed is regarded as a standard signal in a state where timing is not delayed by judging the presence or absence of a vertical synchronous pulse at the timing of first and second count pulses.
SOLUTION: The count pulse P525 or P1050 outputted from a timing generation part 13 through an AND circuit 14 is supplied to the clock terminals of flip flops 16 and 17. The output level of an output terminal Q is decided by the fall of trigger pulses Pt and Ptr. A judged result outputted from an AND circuit 18 is supplied to the data terminal of a flip flop 20. Since a latch pulse La is supplied to the clock terminal of the flip flop 20, the output level of the AND circuit 18, namely, the judged result of standard/non-standard signals can be held. The judged result is supplied to a synchronous interpolation processing part 9.
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Inventors:
Atsushi Ueshima
Application Number:
JP21407496A
Publication Date:
July 27, 2005
Filing Date:
July 26, 1996
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N5/08; H04N5/10; (IPC1-7): H04N5/10; H04N5/08
Domestic Patent References:
| JP556302A | ||||
| JP8065596A |
Attorney, Agent or Firm:
Atsuo Waki
Yasuo Asami
Yasuo Asami
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