To make it possible for a video signal processing circuit to process video signals with a variety of formats, and simplifies the configuration of the video signal processing circuit.

The video signal processing circuit comprises a synchronizing signal generating means (internal vertical synchronizing pulse generating circuit 31) for generating a second synchronizing signal (internal synchronizing vertical pulse 3AV'), on the basis of a display system reference clock signal (3A); a phase comparing means (synchronizing signal comparing circuit 34) for comparing the phase of a first synchronizing signal (detected vertical synchronizing signal 2V) included in a input video signal with that of the second synchronizing signal; and a synchronizing means (phase synchronizing circuit 32) for synchronizing the second synchronizing signal with the first synchronizing signal, when a phase difference that is out of a reference range results from the comparison by the phase comparing means. The second synchronizing signal is generated as a third synchronizing signal (horizontal synchronizing signal 3AH, vertical synchronizing signal 3AV).