SYSTEM LATENCY LEVELIZATION FOR READ DATA

Title:

SYSTEM LATENCY LEVELIZATION FOR READ DATA

Document Type and Number:

Japanese Patent JP2007272929

Kind Code:

A

Abstract:

To provide a memory device equalizing the system read latencies of every memory device in a high speed memory system.

In a high speed memory subsystem, differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and a memory controller results in widely varying system read latencies. The differences in system read latencies of each device are thereby compared, and each memory device is operated with a device system read latency which causes every device to exhibit the same system read latency.

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Inventors:

JANZEN JEFFERY W
KEETH BRENT
RYAN KEVIN J
MANNING TROY A
BRIAN JOHNSON

Application Number:

JP2007182589A

Publication Date:

October 18, 2007

Filing Date:

July 11, 2007

Export Citation:

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Assignee:

MICRON TECHNOLOGY INC

International Classes:

G06F12/00; G11C7/10; G11C7/22; G11C11/407

Domestic Patent References:

JP2000112816A	2000-04-21
JPH1020974A	1998-01-23
JPH10154395A	1998-06-09
JPH103784A	1998-01-06

Foreign References:

WO1998015897A1

1998-04-16

Other References:

JPN6013001025; 直野典彦: 'ダイレクトラムバス技術を使った高速メモリシステムの設計　第８回' Ｉｎｔｅｒｆａｃｅ第２５巻、第１１号, 19991101, ｐ．１８４〜１９５, ＣＱ出版社
JPN6013001597; 中林祥恵: 'ダイレクトラムバス技術を使った高速メモリシステムの設計　第１０回' Ｉｎｔｅｒｆａｃｅ第２６巻、第１号, 20000101, ｐ．１８７〜１９４, ＣＱ出版社

Attorney, Agent or Firm:

Yoshikazu Tani
Kazuo Abe

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