Title:
SYSTEM AND METHOD FOR COMPARATOR HAVING MULTI-STAGE, LOW OFFSET, AND HIGH-SPEED RECOVERY
Document Type and Number:
Japanese Patent JP3683486
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a system and a method for a comparator having multi- stage, low offset, and high-speed recovery.
SOLUTION: An input offset of a nullified amplifier 86 is reduced at a rate substantially equal to a gain of the nullified amplifier 86. An amplifier stage 70 is formed by coupling a main amplifier 72 with the nullified amplifier 86, the input offset voltage of the obtained coupling amplifier is reduced at a rate substantially equal to the product of the gains of the main amplifier 72 and the nullified amplifier 86 and an input signal 74 to the coupling amplifier is amplified according to the gain of the main amplifier 72. Connecting a plurality of the amplifier stages 70 in cascade configures the comparator system for multi-stage, low offset, and high-speed recovery so as to generate a high resolution signal 78 that is amplified in multi-stages.
Inventors:
Bruce Edward Amagine
Michael See W Corn
Scott Wayne
Gerald A. Miller
Mick Mueck
Michael See W Corn
Scott Wayne
Gerald A. Miller
Mick Mueck
Application Number:
JP2000270176A
Publication Date:
August 17, 2005
Filing Date:
September 06, 2000
Export Citation:
Assignee:
ANALOG DEVICES,INCORPORATED
International Classes:
H03K5/08; H03F1/34; H03F3/34; H03F3/45; H03F3/68; H03K5/24; (IPC1-7): H03F3/34; H03F1/34; H03F3/45; H03F3/68; H03K5/08
Domestic Patent References:
| JP2019020A | ||||
| JP9069761A | ||||
| JP4097608A | ||||
| JP7131260A | ||||
| JP5129904A | ||||
| JP60242376A |
Attorney, Agent or Firm:
Atsushi Ichito
Reijiro Ichihigashi
Reijiro Ichihigashi