To provide testing circuit for electronic apparatuses, capable of reducing testing time and cost, without relying on a PLL circuit.

The electronic machinery testing circuit is equipped with the PLL circuit 17, an external clock circuit 18 for outputting a magnification clock signal or an external clock signal corresponding to a test signal state, a frequency-dividing circuit 19 dividing the frequency of the magnification clock signal or external clock signal to form a system clock signal for a logic circuit and a clock signal for an encoder circuit to output them, an input cell 11, a reception circuit 12, a decoder circuit 13, the logic circuit 20 for processing the decoded data corresponding to the system clock signal for the logic circuit by a predetermined logic signal, the encoder circuit 16 for encoding the data processed corresponding to the clock signal for the encoder circuit, a transmission circuit 15 for transmitting the encoded data and an output cell 14.