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Title:
TEXTURE DOPE STRUCTURE SEMICONDUCTOR DEVICE TEXTURE
Document Type and Number:
Japanese Patent JPH05206173
Kind Code:
A
Abstract:

PURPOSE: To provide regularity to arrangement of impurity atom based on quantum dynamics wave characteristics of electron (carrier) by forming a texture dope structure wherein impurity atom is arranged regularly in an electron supply layer.

CONSTITUTION: An electron supply layer 13 is laminated on an undoped GaAs layer 12 in a high mobility transistor (HEMT). A system dope structure 13a which is formed by arranging a plurality of delta doped layers 19 wherein impurity atom is concentratively doped in a direction (y-direction) which crosses at right angles to a proceeding direction (z-direction) of carrier wave, for example, and a spacer layer 13b are provided to an inside of the electron supply layer 13 to form a two-dimensional electron channel 17 in a lower surface of the spacer layer 13b. When intervals x, y, z are properly set based on wave dynamics to arrange impurity atom 18 regularly, scattering by impurity atom can be restrained. Thereby, it is possible to realize high electron mobility and to enable rapidity of a semiconductor operation.


Inventors:
FURUYA KAZUHITO
Application Number:
JP1420992A
Publication Date:
August 13, 1993
Filing Date:
January 29, 1992
Export Citation:
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Assignee:
TOKYO INST TECH
International Classes:
H01L21/335; H01L21/338; H01L29/36; H01L29/737; H01L29/80; H01L29/778; H01L29/78; H01L29/812; (IPC1-7): H01L21/338; H01L29/804; H01L29/812
Domestic Patent References:
JPH01128577A1989-05-22
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)