Title:
THIN FILM MEMORY TRANSISTOR
Document Type and Number:
Japanese Patent JPH04334062
Kind Code:
A
Abstract:
PURPOSE: To obtain a thin film memory transistor capable of reducing writing voltage and erasing voltage.
CONSTITUTION: The title transistor is constituted by arranging an upper electrode 19 and a lower electrode 12 on the upper surface and the lower surface of a semiconductor layer 15, respectively, and arranging an insulating layers 18 and 13 having charge capturing function between the upper surface of the semiconductor layer 15 and the upper gate electrode 19 and between the lower surface of the semiconductor layer 15 and the lower gate electrode 12, respectively.
Inventors:
ONAKA EIICHI
Application Number:
JP10435091A
Publication Date:
November 20, 1992
Filing Date:
May 09, 1991
Export Citation:
Assignee:
CASIO COMPUTER CO LTD
International Classes:
H01L29/78; H01L21/8247; H01L29/786; H01L29/788; H01L29/792; (IPC1-7): H01L29/784; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Takehiko Suzue
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