PURPOSE: To obtain a time axis correcting device having fast response speed by using an absolute address for the write to a memory and using a relative address in response to the phase error amount between a reference synchronizing signal and a reproduced horizontal synchronizing signal for the read.

CONSTITUTION: A reproduced signal for a VTR A/D-converted by an A/D converter 4 is written in a main memory 5 by the reference synchronzing signal HD and a phase locked clock of this signal HD. On the other hand, the amount of phase error between a reproduced horizontal synchronizing signal PBH and the reference signal HD is detected by an H error detector 13 and written in an address memory 14. Further, the read from the main memory 5 is conducted so that the address point of the address memory 14 and the phase of the reference signal HD are made coincident. That is, the write is conducted by using the absolute address in a memory control 11 and the read is performed by the relative address in response to the horizontal synchronizing signal PBH and the reference signal HD.