Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JPH08512421
Kind Code:
A
Abstract:
The invention relates to a semiconductor device with which input signals can be weighted and the weighted input signals can be summed, and which in conjunction with a neuron can be used, for example, as a synapse in a neural network. The device comprises a number of switched capacitances with a common capacitor plate formed by a surface region 3 in a p-type substrate 1. The region 3 is connected to the inverting input of an amplifier 11 whose +input is connected to a reference voltage and whose output 12 supplies the summed output signal. The output 12 can be fed back to the input 3 via switch S. The other plate of the capacitances is formed by an electrode 6a, 6b, 6c, which can be switched between a reference voltage and an input source. The weight factors are stored in the form of electric charges on a floating gate 5a, 5b, 5c, which is provided between each input electrode 6 and the surface region 3. During operation, the input signals are each converted into a depletion charge in the surface region 3 whose value is dependent not only on the input signal but also on the charge on the associated floating gate. The sum of the depletion charges is subsequently stored in an output capacitance 13,3 and read out by means of the amplifier 11.
Inventors:
Widelshofen Franciscus Petrus
Application Number:
JP52881695A
Publication Date:
December 24, 1996
Filing Date:
May 03, 1995
Export Citation:
Assignee:
Philips Electronics Nemrose Fennaught Shap
International Classes:
G06G7/60; G06N3/063; H03K19/08; H03M1/80; (IPC1-7): G06G7/60
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)