Title:
【発明の名称】バス障害時の障害箇所特定装置
Document Type and Number:
Japanese Patent JP2880910
Kind Code:
B2
Abstract:
PURPOSE:To specify a faulty range whether a fault is the one of a bus itself or the one of the bus control part of a processor by providing a bypass part in each processor when the fault occurs in a bus for data transfer in a bus type communication system provided with a control bus for the control of plural processors and the bus for data transfer for data communication between the processors. CONSTITUTION:The bypass parts 41-4n which bypass a transmission control part and a reception control part are added on the processors 1-n provided with transmission control parts 21-2n and reception control parts 31-3n. Each processor performs transmission/reception by using the bus for data transfer 7, and a master processor 1 is equipped with a fault judging part 5 which can detect in which processor the fault occurs by the control bus 6, and brackets the faulty part of the bus by checking whether or not the data transfer is feasible by using the bypass parts of both processors sequentially.
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Inventors:
KONUKI MASATO
Application Number:
JP11232494A
Publication Date:
April 12, 1999
Filing Date:
May 26, 1994
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H04L12/24; H04L12/26; H04L12/40; H04L12/437; (IPC1-7): H04L12/437
Domestic Patent References:
JP293970A | ||||
JP61127246A | ||||
JP4243341A | ||||
JP440503A | ||||
JP5120048A | ||||
JP5466731A | ||||
JP605642A |
Attorney, Agent or Firm:
Naoki Kyomoto