PURPOSE: To constitute the unit stage of a small number of wiring and element by constituting the unit stage of a pair of gates consisting of two coincidence gates, and a coincidence gate and an invertor of one piece each.

CONSTITUTION: In a unit state 200, the pair of the first gates 211 are constituted of NAND gates 21, 22 having respective input terminals and output terminals cross coupling-connected, and in the same way, the pair of the second gates 212 is constituted of NAND gates 23, 24. Also, the output terminals of the gates 21, 22 are connected to other input terminals of the gates 23, 24, respectively, the secnd input terminal of the gates 21, 22 is connected to the output terminal of an NAND gate 25, and the third input terminal is connected to the output terminals of the NAND gates 24, 23, respectively. Also, the input terminal 25a of the gate 25 is connected to a unit stage 100, an input terminal 25b is connected to the output terminal of the gate 21, the output of a unit stage 300 is connected to the fourth input terminal of the gate 22, and the output terminal of the gate 21 is connected to the input of the following stage.