PREPARATION OF SEMICONDUCTOR DEVICE

Japanese Patent JPS58147045

A

PURPOSE:To perfectly make flat the wiring forming surface of upper layer and to improve reliability of device by forming an electrode window and groove corresponding to wiring pattern previously on the SiO2 layer of lower layer and by filling wiring metal therein. CONSTITUTION:The Si3N4 mask 14 is provided to an N<-> epitaxial layer 13 on a P type Si substrate 11 having an N<+> buried layer 12 and it is then etched. After implanting the B ion to a recess, it is oxidized and thereby the layers 18, 19 are formed. Accordingly, a buried bottom surface reaches the buried layer 12 and a P type channel cut 20 is formed at the area under the layer 18. The mask 14 is removed and the surface is covered with a SiO2 film 21, then ion is selectively implanted, followed by the annealing. Thereby, the N<+> collector leadout layer 22, P base 23, P<+> leadout layer 24 and P type resistance layer 25 are formed and are covered with a SiO2 26 layer. The recesses 28, 29 are formed on the film 26 using a resist mask 27 and then a mask 27' is provided again and windows 31-33 are provided on the films 26, 21. The mask 27' is removed and the surface is covered with a non-additive poly-Si 34 and ion is selectively implanted thereto. Thereby, an N<+> emitter 35 and N<++> collector connecting layer 36 are formed. The surface is then polished after covering it with Al 37' and the lower layer wiring 37 buried in the SiO2 film is completed. Thereafter, an isoplaner type IC can be formed by the conventional method.

MONMA YOSHINOBU
ABE RIYOUJI
GOTOU HIROSHI
TABATA AKIRA
FUKUYAMA TOSHIHIKO
SUGISHIMA KENJI

JP2841782A

September 01, 1983

February 24, 1982

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FUJITSU LTD

H01L23/52; H01L21/28; H01L21/302; H01L21/3065; H01L21/3205; (IPC1-7): H01L21/302; H01L21/92

Koshiro Matsuoka

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