Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MEMORY CHIP TESTING DEVICE
Document Type and Number:
Japanese Patent JPS5897668
Kind Code:
A
Abstract:

PURPOSE: To take an effective test of a memory chip having redundant cells, by obtaining a defective cell distribution map used effectively for the relieving of a chip which has defective cells to be relieved.

CONSTITUTION: When even an defective cell is present in each line (row or column), a fail register FREG stores 1, which is used for relieving. A fail cell counter FCCT counts and stores the number of defective cells in each line. When addresses X and Y of a defective cell are new, a fail address recorder FADCX allocates one of linear memories FBLM for defective bit writing on the X side to an address equal to the X in the memory incorporated in the recorder, thereby writing defect information in an address equal to the Y in the FBLM. A fail counter FLC counts up when addresses X and Y are both new to check on whether the counted value exceeds the number of redundant cells or not. When relieving is possible, a defective cell distribution position map is utilized for it.


Inventors:
TAKEMOTO JINICHI
TAKAHASHI MASUO
MAKI KATSUHIKO
Application Number:
JP19512981A
Publication Date:
June 10, 1983
Filing Date:
December 05, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI ELECTR ENG
International Classes:
G01R31/28; G11C29/00; G11C29/44; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Takeo Agata