Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TESTING METHOD OF SEQUENCE CIRCUIT
Document Type and Number:
Japanese Patent JPS60127474
Kind Code:
A
Abstract:

PURPOSE: To enable the detection of inferior operation without missing the same, by providing function for performing a test by strobing the output of testing FF in predetermined timing.

CONSTITUTION: The control part 11a of a tester 1a performs strobing due to CLKIV as timing previous from a second clock signal CLKII and, on the basis of the output thereof, one cycle delayed expected value data DATA2n-1 is sent out other than expected value data DATA1n, DATA2n to perform the testing of DEF2. In addition, the control part 11a controls a delay circuit DL14c and a selector circuit MPX15c to send out CLKIV to a comparator citcuit 13b and collates the Q-output of FF2 with separate DATA2n-1 on the basis of CLKIV and, when no coincidence is obtained, abnormal operation is judged.


Inventors:
KUDOU YOUICHI
Application Number:
JP23451383A
Publication Date:
July 08, 1985
Filing Date:
December 13, 1983
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
G06F11/16; G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Koshiro Matsuoka



 
Previous Patent: JPS60127473

Next Patent: INTEGRATED CIRCUIT TESTING APPARATUS