PURPOSE: To widely secure the safely operating region DCASO particularly of a power MOSFET by a method wherein a p type region is diffused to the surface of an Si substrate with a poly Si layer as a mask, next the side end of the Si layer being partly removed into a gate, and an n+ type region serving as the source being then diffused to the surface of the p type region with this Si layer as a mask.

CONSTITUTION: An Si3N4 film 7 is removed by etching with thermal phosphoric acid, etc., a masking member 8 of SiO2 film or the like is formed at part of the surface of a diffusion window, and then the n+ type region 5 serving as the source of a diffusion width d2(d2d1) is formed by ion implantation of As or P and diffusion. At this time, n+ type diffusion is carried out through the diffusion window of the state that the poly Si layer 3 shifts to the channel side by d0. Then, an insulation film 9 of PSG, etc. is deposited over the entire surface and contact-photoetched, thereafter Al is evaporated, thus forming an Al electrode 6 contacting by low resistance with the region 5 and with part of a p type region 4 adjacent thereto, and then patterned to completion.