Title:
DATA TRANSFER CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS60558
Kind Code:
A
Abstract:
PURPOSE: To speed up DMA by making bus occupation exclusion control by a lower unit itself when the lower unit makes DMA through a common bus in interlace mode.
CONSTITUTION: Prior controlling mechanism for lower units-1,-2 is not provided in a C-BUS controlling device 12. Instead of it, the lower unit-1 generates a transfer permission signal TA to the lower unit-2 when the unit-1 itself has no data transfer request. When the unit-1 has data transfer request to the lower unit-2, and received the transfer permission signal TA, outputs a C-BUS occupation request signal REQ, and when the transfer permission signal TA becomes off, completes data transfer in specified time.
Inventors:
KOBAYASHI MASAAKI
KAMIDATE MORIHIRO
II TOSHIAKI
KISHINO TAKUMI
KAMIDATE MORIHIRO
II TOSHIAKI
KISHINO TAKUMI
Application Number:
JP10864983A
Publication Date:
January 05, 1985
Filing Date:
June 17, 1983
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F13/37; G06F13/28; (IPC1-7): G06F13/28; H04L11/00
Attorney, Agent or Firm:
Minoru Aoyagi
Next Patent: BUFFER CONTROLLING SYSTEM