PURPOSE: To prevent defective access to a memory element, by reducing the level of a common data line at standby to suppress a peak value of noise generated from the common data line.
CONSTITUTION: A memory element M of a memory array 3 consists of an FAMOSFET having a floating gate electrode and a control gate electrode. When a read circuit 6 is made active with a signal from a control circuit 8, the storage data of one element M1 selected on a word line W and a data line D is readout and led to a terminal I/O. In this case, a low level signal CE is applied to a gate of an MOSFETQ10 from the circuit 6 at the standby to turn off the Q10, and Q6, Q7 are turned on because a voltage from a voltage dividing circuit 9 is applied to the gate of them, Q2, Q3 are turned off and a current to a common data line CD is decreased. As a result, after a chip enable signal -CE is changed from high to low, the access time to the data readout is reduced.
FUKUDA MINORU
YAMATANI SHIGERU
| JPS57127989A | 1982-08-09 |
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