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Patent Searching and Data


Title:
UV TAPE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE
Document Type and Number:
Japanese Patent JP2003007743
Kind Code:
A
Abstract:

To provide a method for manufacturing a semiconductor integrated circuit package capable of safely and efficiently executing a step of dicing of manufacturing steps of the integrated circuit package.

The method for manufacturing the semiconductor integrated circuit package comprises a step of mounting a plurality of integrated circuit chips 2 on a mounting board 1, a step of electrically connecting each chip 2 to a predetermined terminal on the board 1 by wiring, a step of molding the plurality of wired chips 2 by a molding resin, and a step of adhering a UV tape 6 to the board 1 by opposing a protrusion 7 of the tape 6 in which the protrusions 7 substantially equal to a thickness of the molding resin 5 are formed, to a part corresponding to an outer periphery in which the resin 5 is not provided on the board 1.


Inventors:
TSURUSAKI NOBUYA
SAWAMOTO SHUICHI
Application Number:
JP2001189150A
Publication Date:
January 10, 2003
Filing Date:
June 22, 2001
Export Citation:
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Assignee:
MITSUMI ELECTRIC CO LTD
International Classes:
C09J7/02; C09J201/00; H01L21/301; H01L21/56; (IPC1-7): H01L21/56; C09J7/02; H01L21/301