VERTICAL ELECTRICAL INTERCONNECTIONS IN STACK

Title:

VERTICAL ELECTRICAL INTERCONNECTIONS IN STACK

Document Type and Number:

Japanese Patent JP2008182252

Kind Code:

A

Abstract:

To provide a memory and/or data processing device having at least two stacked layers that are supported by a substrate or forming a sandwiched self-supporting structure.

The layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.

Inventors:

NORDAL PER-ERIK
GUDESEN HANS GUDE
LEISTAD GEIRR I
GUSTAFSSON GOERAN

Application Number:

JP2008030748A

Publication Date:

August 07, 2008

Filing Date:

February 12, 2008

Export Citation:

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Assignee:

THIN FILM ORUDOKO ASA

International Classes:

H01L21/3205; H01L21/8246; H01L21/00; H01L21/60; H01L21/768; H01L23/522; H01L25/065; H01L27/00; H01L27/10; H01L27/105; H01L

Attorney, Agent or Firm:

Hideto Asamura
Hajime Asamura
Hayashi Zouzo

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