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Title:
VERTICAL FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH10173168
Kind Code:
A
Abstract:

To improve the breakdown voltage of a vertical field effect transistor by forming the passage of a current when a drain area and a P-type base area are reversely biased and yield so that the passage can pass through the edge section of the bottom face of a high-concentration P-type base area from the flat section of the P-type base area.

The depth difference L3 between a P-type base area 6 and a high-concentration base area 5A is adjusted so that an avalanche current can flow through the edge section of the bottom section of the base area 5A from the flat section on the bottom of the base area 6 when the difference L3 becomes ≤0.5μm. Therefore, current routes 12A and 12Ar become shorter than the conventional example. Since the routes become shorter at the sections passing through the base area 6 having a high resistance, the base potential of a parasitic NPN transistor which uses a low-concentration N-type drain area 8, the P-type base area 6, and the high-concentration P-type base area 5A as a collector, base, and emitter, respectively, becomes lower and the current amplification factor of the transistor drops. Therefore, the breakdown voltage of the transistor can be improved when the transistor is driven in a state where a dielectric load is connected to the transistor.


Inventors:
KAWAHARA MINORU
Application Number:
JP33196596A
Publication Date:
June 26, 1998
Filing Date:
December 12, 1996
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L29/78; H01L29/10; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)