Title:
VOLTAGE SUBTRACTING CIRCUIT, VOLTAGE AMPLIFYING CIRCUIT, VOLTAGE DIVIDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3392696
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a voltage subtracting circuit in which any resistance can be unnecessitated, a high impedance can be obtained, use with high precision and high frequencies can be attained, and the influence of a process can be escaped.
SOLUTION: A voltage subtracting circuit is provided with a constant current source 1, first MOS transistor pair 2 whose one end is connected with a power supply voltage terminal, and second transistor pair 3 whose one end is connected with the constant current source 1. A first differential input voltage is impressed between the gate terminals of the first transistor pair 2, and a second differential input voltage is impressed between the gate terminals of the second transistor pair 3. Output terminals V1 and V2 are connected with the connections of the first and second transistor pairs 2 and 3, and difference voltages between the first differential input voltage and a differential voltage proportional to the second differential input voltage are outputted from those connections V1 and V2. This circuit is not provided with a resistance so that integration can be simply attained, the influence of Vth or the like can be escaped, and precision can be made high.
Inventors:
Shuji Koike
Application Number:
JP8969997A
Publication Date:
March 31, 2003
Filing Date:
April 08, 1997
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06G7/14; H03F3/45; (IPC1-7): G06G7/14
Domestic Patent References:
| JP62293385A | ||||
| JP457179A | ||||
| JP6103389A | ||||
| JP6188735A | ||||
| JP61226882A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)