PURPOSE: To reduce turn-around-time and improve a yield rate, by arranging a plurality of gate array blocks after arraying them which are separated by wiring regions having wiring in wafers and forming integrated circuit systems which are connected one another through wiring in the wafers of the wiring regions.

CONSTITUTION: An integrated circuit wafer l where gate array blocks 5 of a plurality of chip-scales are arrayed at the surface of the wafer l through wiring regions 3X and 3Y are formed by a mass-production process and a plurality of integrated circuit blocks which are necessary to construct required systems are formed through a master slice system by using the gate array blocks 5. In this way, as manufacturing moves commenced from the presentation of functions required by the systems and ended by completion of waferscale integrated circuit equipped with these systems are drastically reduced, considerable curtailment of turn-aroundtime of the wafer-scale integrated circuit is realized. Further, a yield rate and reliability as well are improved by applying a mass production process to the production process prior to the master slice system.