PURPOSE: To enable small-scale and high-accuracy weighted addition and to easily provide various arithmetical forms by outputting the balanced voltage of parallel resistance in common.
CONSTITUTION: A weighted adder circuit A parallelly connects plural inductances L1-L3 corresponding to the common output (such as an output voltage VOUT as a representative) and input voltages V1-V3 are impressed to the other terminals of the inductances L1-L3. Then, the common output of the weighted adder circuit is connected through capacitance C to circuits in following steps. Namely, the weighted adder circuit defines the balanced voltage of parallel inductances as the common output. Therefore, the output voltage VOUT is always turned to the weighted added result with the changes of input voltages V1-V3 and the simulated result of the output voltage VOUT is coincident with a theoretical value calculated by an expression. Then, the higher an input signal frequency is increased, the more energy consumption is reduced.
YOU IKOU
UIWATSUTO UONWARAUIPATSUTO
TAKATORI SUNAO
YAMAMOTO MAKOTO
SHARP KK