Title:
WIRING ESTIMATION EQUIPMENT AND ITS USING METHOD
Document Type and Number:
Japanese Patent JP3284731
Kind Code:
B2
Abstract:
PURPOSE: To realize electromigration resistance estimation excellent in accuracy by defining temperature caused by heat generation of a wiring at the time of applying a current of high density, with high precision.
CONSTITUTION: N+ layers 21 and P+ layers 23 of contact and diode electrodes 25 are formed on an N layer formed on a P-type silicon substrate by a vapor growth method, a P layer 22 formed on the substrate by a heat diffusion method, and two aperture parts of a field oxide film formed on the surface of the layer 22. A first Al wiring 26 and a first W wiring 27 on the surface of the field oxide film, a second Al wiring 28 and a second W wiring 29 on the surface of an interlayer insulating film, and a passivation film with which the surface of a chip is covered are formed.
Inventors:
Koichi Nishimura
Application Number:
JP2793494A
Publication Date:
May 20, 2002
Filing Date:
February 25, 1994
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Domestic Patent References:
| JP290646A | ||||
| JP2112254A | ||||
| JP63190353A | ||||
| JP567664A | ||||
| JP6351654A | ||||
| JP6066442A | ||||
| JP3211855A | ||||
| JP4154142A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)