Title:
An interface for a wafer inspection, and wafer test equipment
Document Type and Number:
Japanese Patent JP5952645
Kind Code:
B2
Abstract:
A wafer inspection interface 40 includes a probe card 43 including probes 43b provided on a surface facing a wafer W; a pogo frame 42 that supports a surface of the probe card 43 opposite to the surface on which the probes 43b are provided; a table-shaped chuck member 45 facing the probe card 43 with the wafer W therebetween; a cylindrical bellows 46, configured to seal a space between the chuck member 45 and the pogo frame 42, having one end fastened to the pogo frame 42 and a lower flange 46b at the other end to be contacted with the chuck member 45; a length adjusting device that adjusts a length of the bellows 46; a guide member 47 that guides a movement of the bellows 46; and a decompression path 51 that decompresses the space between the chuck member 45 and the pogo frame 42.
Inventors:
Hiroshi Yamada
Application Number:
JP2012128712A
Publication Date:
July 13, 2016
Filing Date:
June 06, 2012
Export Citation:
Assignee:
東京エレクトロン株式会社
International Classes:
H01L21/66; G01R31/28
Domestic Patent References:
| JP2001203244A | ||||
| JP2001338952A | ||||
| JP2000164647A |
Foreign References:
| WO2013183740A1 |
Attorney, Agent or Firm:
Another role Shigehisa
Satoshi Muramatsu
Satoshi Muramatsu
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