Title:
Methods, devices and systems for controlling the power consumption of unused hardware of linked interfaces
Document Type and Number:
Japanese Patent JP6321194
Kind Code:
B2
Abstract:
In an embodiment, a plurality of hardware buffers each may store information associated with one or more virtual channels. In turn, a configuration logic is to determine an identifier corresponding to a maximum number of virtual channels commonly supported by first and second devices coupled via a link and to obtain a control value based on the identifier. A gate logic coupled to the configuration logic is to provide an operating voltage to corresponding ones of the hardware buffers based on the control value. In this way, the operating voltage can be withheld from at least one of the hardware buffers when the maximum number of virtual channels is less than the plurality of hardware buffers. Other embodiments are described and claimed.
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Inventors:
Vaganes Waran, Ragavan
Application Number:
JP2016553359A
Publication Date:
May 09, 2018
Filing Date:
March 20, 2014
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F1/32; G06F3/00
Domestic Patent References:
| JP2013025416A | ||||
| JP2010044569A | ||||
| JP2013528970A |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki