Title:
A semiconductor device, a display, and electronic equipment
Document Type and Number:
Japanese Patent JP5940130
Kind Code:
B2
Abstract:
To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.
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Inventors:
Atsushi Umezaki
Application Number:
JP2014227647A
Publication Date:
June 29, 2016
Filing Date:
November 10, 2014
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; G09F9/30; G09G3/20; G09G3/36; H01L29/786
Domestic Patent References:
| JP2007250052A | ||||
| JP2007123861A | ||||
| JP2008130139A |
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